Search - quartus ii

[Other resource] quartus

Description: quartus II中文用户教程，Quartus II 用户指南，很有好处的哦！
Platform: | Size: 845513 | Author: 谌洪东 | Hits:

[Develop Tools] Quartus

Description: 上传一份cpld 开发工具，Quartus II 中文教程.pdf，供学习参考。
Platform: | Size: 893121 | Author: chaidong | Hits:

[Documents] Quartus II chinese

Description: TCP或UDP协议通信-TCP or UDP communications
Platform: | Size: 857088 | Author: 明明 | Hits:

[VHDL-FPGA-Verilog] Nios II处理器中文参考手册

Description: nios2软件开发手册中文版第8章_MicroC_OSII_tutorial，翻译的不错值得一看-nios2 software development manuals Chinese version of Chapter 8 _MicroC_OSII_tutori al translation of a true eye-catcher
Platform: | Size: 259072 | Author: wang | Hits:

[VHDL-FPGA-Verilog] std_cf_2c35

Description: 这个是基于NIOS II的FPGA平台的一个CF卡的接口模块，是在Quartus II下的完整工程包-NIOS II FPGA platform a CF card interface module, Quartus II is the complete package works
Platform: | Size: 399360 | Author: 佴立峰 | Hits:

[VHDL-FPGA-Verilog] ref-ualaw

Description: A率/u率压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate/u rate compression and decompression of the IP core,. By AHDL# languages, and the Quartus II MaxplusII use, the source code encryption.
Platform: | Size: 119808 | Author: zhangkun | Hits:

[Software Engineering] quartus_Chinese_Introduction

Description: quartus 软件应用中文教程，包含一些高级的用法等。-quartus Chinese Directory software applications, including some senior usage, and so on.
Platform: | Size: 6616064 | Author: Frank | Hits:

[VHDL-FPGA-Verilog] CNTlum

Description: 使用Windows7 系统，quartus ii 9.1 软件，Verilog 语言 0到9的计数，并且亮度逐渐增大(count from 0 to 9,and the lum become more and more high)
Platform: | Size: 1354752 | Author: Eris | Hits:

[Windows Develop] 基于Quartus-II-的FPGACPLD开发

Description: 基于Quartus-II-的FPGACPLD开发(Development of FPGACPLD based on Quartus-II)
Platform: | Size: 6297600 | Author: VVVX | Hits:

[Other Embeded program] adder

Description: 此电路是一个基于Quartus II 的加法器，由两个半加器组成。(The circuit is an adder based on Quartus II, consisting of two adder.)
Platform: | Size: 70656 | Author: 小竹塘 | Hits:

[Other] 数电综合实验工程文件

Description: 像素鸟游戏代码，平台为quartus II，实现功能为简易像素鸟游戏。(Pixel bird game code)
Platform: | Size: 1186816 | Author: lte | Hits:

[VHDL-FPGA-Verilog] HEX2MIF

Description: QUARTUS II SRAM/ROM初始化需要的HEX文件与Keil产生的HEX格式不同；该Modelsim程序，将Keil产生的Hex转换成，Quartus可以是识别的MIF格式；(The QUARTUS II SRAM/ROM initialization needs HEX files which are different from those generated by Keil. The Modelsim program converts Hex generated by Keil to Quartus, which can be recognized as the MIF format.)
Platform: | Size: 1024 | Author: MCUMaster | Hits:

[Embeded-SCM Develop] quanjiaqi

Description: 程序的功能是在quartus II环境下实现全加器的功能。(The function of the program is to implement the full adder function in Quartus II environment.)
Platform: | Size: 335872 | Author: 郦 | Hits:

[VHDL-FPGA-Verilog] Password lock

Description: 一个 Quartus II 工程，芯片为EP3C55F484C8，是一个简单的保险箱密码锁。包含分频器、键盘去抖、8选1选择器、扬声器模块、动态扫描模块等多个模块。主要功能： 1. 保险箱上设有密码输入和钥匙锁双重保险。 2. 当密码输入正确后，左边的指示灯亮，此时插入钥匙即可打开保险箱；当密码输入错误后，右边的指示灯亮，发出报警信号，此时需要重新输入密码。 3. 保险箱的密码可根据需要随时更换。(A Quartus II project, the chip is EP3C55F484C8, is a simple safe lock. It includes frequency divider, keyboard shake, 8 selector 1 selector, loudspeaker module, dynamic scanning module and so on. Main functions: 1. the safety box is provided with double insurance of password input and key lock. 2. when the password is correct, the indicator on the left is bright. At this time the key can be opened to open the safe. When the password is wrong, the indicator on the right is bright and the alarm signal is sent. The password is reentered at this time. 3. the cipher's password can be changed at any time.)
Platform: | Size: 4777984 | Author: yves05 | Hits:

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[Other resource] quartus

[Develop Tools] Quartus

[Documents] Quartus II chinese

[VHDL-FPGA-Verilog] Nios II处理器中文参考手册

[VHDL-FPGA-Verilog] std_cf_2c35

[VHDL-FPGA-Verilog] ref-ualaw

[Software Engineering] quartus_Chinese_Introduction

[VHDL-FPGA-Verilog] CNTlum

[Windows Develop] 基于Quartus-II-的FPGACPLD开发

[Other Embeded program] adder

[Other] 数电综合实验工程文件

[VHDL-FPGA-Verilog] HEX2MIF

[Embeded-SCM Develop] quanjiaqi

[VHDL-FPGA-Verilog] Password lock

[Develop Tools] Quartus II 9.1 (64-Bit)可用的破解器

[VHDL-FPGA-Verilog] Quartus II 6.0 Handbook

[VHDL-FPGA-Verilog] Quartus II 7.1 Handbook

[VHDL-FPGA-Verilog] Quartus II 7.2 Handbook

[VHDL-FPGA-Verilog] Quartus II 8.0 Handbook

[VHDL-FPGA-Verilog] Quartus II 8.1 Handbook

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